An extract on #osmanlispor
With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95.
The definition of constants in Verilog supports the addition of a width parameter. The basic syntax is:
<Width in bits>'<base letter><number>
12'h123 Hexadecimal 123 (using 12 bits)
20'd44 Decimal 44 (using 20 bits 0 extension is automatic)
4'b1010 Binary 1010 (using 4 bits)
6'o77 Octal 77 (using 6 bits)
The fork/join pair are used by Verilog to create parallel processes. All statements (or blocks) between a fork/join pair begin execution simultaneously upon execution flow hitting the fork. Execution continues after the join upon completion of the longest running statement or block between the fork and join.
The way the above is written, it is possible to have either the sequences "ABC" or "BAC" print out. The order of simulation between the first $write and the second $write depends on the simulator implementation, and may purposefully be randomized by the simulator. This allows the simulation to contain both accidental race conditions as well as intentional non-deterministic behavior.
Notice that VHDL cannot dynamically spawn multiple processes like Verilog.
Tips About Using Verilog Free verilog program example and tips for Advanced User
The Development Channel (26 April 2015). FPGA Course. YouTube.
Johan Sandstrom (October 1995). "Comparing Verilog to VHDL Syntactically and Semantically". Integrated System Design. EE Times. Sandstrom presents a table relating VHDL constructs to Verilog constructs.
Verilog Tutorial Beginners tutorial.
Asic-World Extensive free online tutorial with many examples.
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AllHDL Verilog for tutorial.
Verilog Tutorial Verilog RTL Tutorial with detailed digital design concepts and examples.
Qualis Design Corporation (20 July 2000). "Verilog HDL quick reference card" (PDF). 1.1. Qualis Design Corporation.
Online Verilog-1995 Quick Reference Guide Stuart Sutherland of Sutherland HDL, Inc.
Online Verilog-2001 Quick Reference Guide Stuart Sutherland of Sutherland HDL, Inc.
Misc EDA Utilities Free Verilog Parser and utilities e.g. verilog2vhdl, vhdl2verilog, verilog2systemc, verilog2ipxact, testbench generator and more
EDA Playground (11 November 2013). Verilog Tutorials. YouTube. Verilog tutorials focusing on hands-on coding and debugging
EDA Playground Free web browser-based Verilog IDE
Verilog Online Help Free Verilog Language Reference Guide
Verilog Programs Verilog programs